1. Field of the Invention
The present invention relates to circuits, and, more particularly, to accurate compensation of analog offset values and to accurate digital-to-analog signal conversion.
2. Description of the Related Art
All analog circuits exhibit some output offset voltage VOS, due to inherent mismatch of transistors. For example, a typical problem associated with operational amplifiers is that of a fixed offset voltage VOS. This error appears as a fixed deviation in the expected output due to imbalances in the operational amplifier. Even when an operational amplifier""s two input voltages are equal, the output node has a voltage value offset from zero. Such offset becomes especially problematic where low level signals are utilized. In order to increase the precision of such operational amplifiers and other analog circuits, it is necessary to compensate for such offset.
There are several techniques to reduce or eliminate offset in analog circuits. For example, laser thin-film resistor trimming at the time of manufacture and fuse-link zapping to adjust resistor sizes each provide some measure of correction for VOS Digital-to-analog converters (DACs) are typically adjusted or trimmed at the time of manufacture to minimize integral nonlinearity (INL) and differential nonlinearity (DNL) errors. Variable resistances may be used to compensate for VOS, but the use of such variable resistances becomes problematic when such resistances are integrated with the compensated circuit. Such problems arise, for example, because manipulation of the variable resistance becomes difficult, and the compensating resistor is subject to ambient conditions in the integrated circuit. Calibration can also be used to correct for VOS. Calibration is typically performed on demand rather than at the time of manufacture.
DACs with successive approximation register (SAR) control have been used to create analog-to-digital converters (A/D converters or ADCs) and have been used in many integrated and discrete calibration schemes. For example, the TLC4501 operational amplifier available from Texas Instruments, Incorporated of Dallas, Tex. includes VOS calibration using a DAC. However, present techniques which operate with a successive approximation register in a feedback loop for calibration are dependent upon the accuracy of the DAC in the feedback loop.
One factor that determines the accuracy of a DAC is resolution. The resolution of a DAC is defined by the smallest average change possible in the output analog signal. The resolution of a DAC is determined by the total number of digital codes and the full scale DAC output. DAC linearity is usually specified in terms of the least significant bit (LSB) of the DAC. For example, in the context of voltage, an exemplary DAC may have a full scale range from ground to a reference voltage VREF (e.g., a full scale range having a magnitude of VREF). An N-bit input digital code allows for 2N quantization levels, or more precisely 0 to 2Nxe2x88x921 steps between zero and VREF. Thus, the minimum change that a DAC can resolve is a step voltage of VREF/2N. This minimum step voltage defines the resolution of the DAC and is commonly referred to as the least significant bit or LSB of the DAC. That is, the least significant bit is equal to the full-scale range of the DAC divided by the number of steps. Thus, the output range of an N-bit DAC is equally divided into 2N units, and one least significant bit (LSB) change in the input digital word makes the analog output voltage change by VREF/2N. As the number of bits increases, the step size (i.e., the LSB) decreases, thereby increasing the accuracy of the system when a conversion is made between an analog and digital signal.
Another factor that determines the accuracy of a DAC is linearity. Integral linearity is a measure of linearity over the entire conversion range. Differential linearity is the linearity between code transitions (e.g., linearity of each step). Integral linearity is a measure of the monotonicity of the DAC. A DAC is said to be monotonic if increasing input codes result in increasing output values. Differential nonlinearity (DNL) is a measure of the deviation of the actual DAC output step from the ideal step of VREF/2N (i.e., 1 LSB). The accuracy in linearity values of a DAC are typically specified in the DAC""s data sheet in units of the LSB. Because linearity can vary with temperature, linearity values are often specified at particular temperature values.
Thus, a single DAC is limited by its resolution and nonlinearities and is typically adjusted, trimmed or otherwise calibrated as discussed above.
It has been discovered that a composite DAC employing multiple independent DACs may be used to more precisely compensate for offset voltage. Such a configuration provides the advantage that a full calibration range may be maintained while increasing the accuracy of the digital-to-analog conversion. For example, the range of a first DAC determines the range of calibration while the presence of a successive, more accurate, independent DAC or DACs determines the accuracy of the calibration. Such a configuration advantageously minimizes integral and differential nonlinearity errors while not requiring adjustment or trimming of the DACs. Such a configuration provides the further advantage of more precise on-chip calibration which eliminates the need for trimming or other adjustment.
An on-chip calibration of analog offset is advantageously provided using an SAR-based structure which implements a calibration operation to adjust a composite DAC which in turn adjusts the input-referred offset of an analog circuit such as an amplifier. The accuracy of the calibration is determined by the resolution and accuracy of the DAC employed in the calibration operation. By using a composite DAC, a structure and method are provided to reduce the error of the calibration below the error of a single, wide-range DAC while maintaining the full calibration range of the wide-range DAC and without requiring the adjustment or trimming of the DAC(s).
For example, a first DAC of a composite DAC may be operated to calibrate an analog signal to within a first DAC error of a target value. A second DAC of the composite DAC may be operated to calibrate the analog signal to within a second DAC error of the target value after the first DAC has been operated. The second DAC has a range less than the range of the first DAC and greater than the error of the first DAC. The composite DAC including the first and second DACs has the range of the first DAC and the error of the second DAC. The process may be repeated with subsequent DACs. Thus, a composite DAC including first, second and third DACs has the range of the first DAC and the error of the third DAC. Generally, a composite DAC has the range of the first DAC and the error of the last DAC in a series of successively operated DACs.
In one embodiment of the invention, a composite digital-to-analog converter (DAC) includes a first DAC and a second DAC. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range of the second DAC is less than the first range of the first DAC. The second range of the second DAC is greater than the first error of the first DAC. The second error of the second DAC is less than the first error of the first DAC. The composite DAC has a composite range and a composite error. The second DAC is coupled to minimize the composite error such that the composite range of the composite DAC is the first range and the composite error of the composite DAC is the second error.
In another embodiment of the invention, an apparatus includes a composite DAC. The composite DAC includes a first DAC, a second DAC and a selection circuit. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range is less than the first range and more than the first error. The second DAC is coupled to minimize error of the composite DAC such that the composite DAC has the first range and the second error. The selection circuit is coupled to the first and second DACs for alternately selecting one of the first and second DACs.
In another embodiment of the invention, a method of minimizing analog circuit offset is provided. The method includes the following: operating a first DAC to calibrate an analog signal to within a first DAC error of a target value; and operating a second DAC to calibrate the analog signal to within a second DAC error of the target value after operating the first DAC. The second DAC has a range less than a range of the first DAC and greater than the first DAC error.